Modern integrated circuits include a vast amount of synchronized components such as processors, memory units, logic gates, flip-flops, peripherals, and the like. In many cases different components receive different clock signals that are not synchronized to each other. This can result, for example, from one of the following reasons: (i) different synchronized components operate at different frequencies, (ii) modern power reduction techniques involve partitioning the integrated circuit to multiple frequency domains and altering the clock signals provided to each frequency domain, (iii) clock distribution networks and clock generators have a limited capability to provide strong and balanced clock signals to many synchronized components.
The various synchronized components can be connected to each other by lines and even buses. Proper reception of information that is conveyed over such buses requires to synchronize the transmission and reception of information over the buses. The following patents and patent applications, all being incorporated herein by reference, illustrate some synchronizing methods: PCT patent application international publication number WO 96/41267° F. Mote, U.S. Pat. No. 6,636,907 of Gaillard et al., U.S. Pat. No. 4,011,465 of Alvarez, and U.S. patent application publication number 2004/0066879 of Gabara.
Various prior art methods and devices are characterized by a long synchronization period. There is a need to provide an efficient device having synchronizing capabilities and an efficient method for synchronizing a transmission of information over a bus.